Index of Lecture Slides

Active and EnabledModesPDF FileHTML FileMS-Word File

Addressing Modes in the Boz-5 PDF File HTML File MS–Word File
ALU Structure PDF File HTML File MS–Word File
Assembly Language for the Boz-5 PDF File HTML File MS–Word File
Assessing Computer Performance PDF File HTML File MS–Word File

Boolean Algebra and Gates PDF File HTML File MS–Word File

Cache Coherence PDF File HTML File MS–Word File
Cache Memory Organization PDF File HTML File MS–Word File
Computer Architecture : Overview PDF File HTML File MS–Word File
Connecting Registers to Busses PDF File HTML File MS–Word File
Control Unit : Overview PDF File HTML File MS–Word File
Coprocessors PDF File HTML File MS–Word File
CPU Bus Structure PDF File HTML File MS–Word File
The Cray Supercomputers PDF File HTML File MS–Word File

Data Representation PDF File HTML File MS–Word File
Design with Real Devices PDF File HTML File MS–Word File
Digital Circuit Elements PDF File HTML File MS–Word File
Digital Circuits and
Boolean Expressions PDF File HTML File MS–Word File
Disk Basics PDF File HTML File MS–Word File

      Early Computers PowerPoint Slides
Encoders and Decoders PDF File HTML File MS–Word File

Flip Flops : Introduction PDF File HTML File MS–Word File
Flip–Flops :Basic IdeasPDF File HTML File MS–Word File
      Floating Point Numbers PDF File HTML File MS–Word File
The Full Adder PDF File HTML File MS–Word File

Hardwired Control Unit PDF File HTML File MS–Word File

The Instruction Set Architecture PDF File HTML File MS–Word File
ISA Micro–Operations PDF File HTML File MS–Word File
Interrupt Handling PDF File HTML File MS–Word File
I/O Strategies PDF File HTML File MS–Word File

Karnaugh Maps PDF File HTML File MS–Word File

Major State Register : Sequencing PDF File HTML File MS–Word File
Memory Basics PDF File HTML File MS–Word File
       Memory Basics (without Big Picture)        PDF File HTML File MS-Word File
Microprogrammed Control Unit PDF File HTML File MS–Word File
Modern Computers PDF File HTML File
MS–Word Part 1 MS–Word Part 2
Modulo–4 Up/Down Counter PDF File HTML File MS–Word File
More Secure OS : Design Issues PDF File HTML File MS–Word File
      Multicore Processors & the Power Wall    PDF File HTML File MS-Word File
Multiplexers and Demultiplexers PDF File HTML File MS–Word File
Multiprocessors (Lecture 1) PDF File HTML File MS–Word File
Multiprocessors (Lecture 2) PDF File HTML File MS–Word File
Multiprocessors (Lecture 3) PDF File HTML File MS–Word File

Network Support and the NIC PDF File HTML File MS–Word File

Other Circuit Elements PDF File HTML File MS–Word File

Packed Decimal Numbers PDF File HTML File MS–Word File
PCI Express PDF File HTML File MS-Word File
Pipelining and Superscalar Designs PDF File HTML File MS–Word File
The Power Wall & Multicore Processors PDF File HTML File MS-Word File

RISC and CISC Designs PDF File HTML File MS–Word File

Sequential Circuit Overview PDF File HTML File MS–Word File
Sequence Detector :Design Example PDF File HTML File MS–Word File
Standard Boolean Forms PDF File HTML File MS–Word File
Subroutine Linkage PDF File HTML File MS–Word File
Support for Security PDF File HTML File MS–Word File
System Bus Fundamentals PDF File HTML File MS–Word File

Traffic Light : Design Example PDF File HTML File MS–Word File
Two’s–Complement Integers PDF File HTML File MS–Word File